Computer Architecture: A Quantitative Approach_03

Computer Architecture: A Quantitative Approach 学习笔记。搭配普林斯顿大学 Comparch 课程在啃。

Lecture 03. Cache Review

Memory Hierarchy

Register/Latch Register file SRAM DRAM
capacity low high
latency low high
bandwidth high low

DRAM: most dense.

Bandwidth: the number of accesses per unit time.
Bandwidth-delay product: the amount of data that can be in flight at the same time.
Long latencies mean large bandwidth-delay products which can be difficult to saturate, meaning bandwidth is wasted.

Basic Cache Knowledge

cache block / cache line: exploit the spatial locality.
//////////What’s the difference between cache block and cache line?
Cache line typically includes the tag information.
Basic Cache Algorithm for a Load:

When cache hits, we also need to check the valid bit.

Block Placement

Fully Associative, (n-way) Set Associative, Direct Mapped.

Block Identification

Tag is used to compare against the memory tag to figure out whether the cache hits.
Index: the mark of the set.
Offset: the location of the data in the block.

Block Replacement

Random, Least Recently Used (LRU), FIFO, Round-Robin, Not Most Recently Used (NMRU)

Write Strategy

Cache Hit

  • Write Through
  • Write Back: dirty bit

Cache Miss

  • No Write Allocate: only write to main memory.
  • Write Allocate: fetch block into cache, then write.

Common Combinations

  • Write Through & No Write Allocate
  • Write Back & Write Allocate