Computer Architecture: A Quantitative Approach_01

Computer Architecture: A Quantitative Approach 学习笔记。搭配普林斯顿大学 Comparch 课程在啃。

Lecture 01. Introduction, Instruction Set Architecture, and Microcode

Parallelism

  • Instruction Level Parallelism
    • Superscalar
    • VLIW
  • Long Pipelines (Pipeline Parallelism)
  • Advances Memory and Caches
  • Data Level Parallelism
    • Vector
    • GPU
  • Thread Level Parallelism
    • Multithreading
    • Multiprocessor
    • Multicore
    • Manycore

Architecture versus Microarchitecture

Computer architecture is all about tradeoffs. “Architecture” / Instruction Set Architecture provide programmer an abstract machine model (no bussiness with implemention). The change of architecture will influence the application / microarchitecture, but also you can make different design decisions and tradeoffs on how to go about implementing a particular instruction set architecture.

“Architecture” / Instruction Set Architecture (ISA)

  • Programmer visible state (Memory & Register)
  • Operations (Instructions and how they work)
  • Execution Semantics (interrupts)
  • Input / Output
  • Data Types / Sizes

Microarchitecture / Organization

  • Tradeoffs on how to implement ISA for some metric (Speed, Energy, Cost)
  • Examples: Pipeline depth, number of pipelines, cache size, silicon area, peak power, execution ordering (in order / out of order), bus widths, ALU widths.

ISA Characteristics

Machine Models

operands: the data value you’re going to operate on with a single instruction of the processor and the results are where are the data that gets calculated, and where does it go.
machine models: stack, accumulator, register-memory, register-register. 反正就还是那几种指令对应的机器模型。

“2 or 3” means some architectures or architectural models don’t necessarily name the resultant, or the result location.

stack: each push/pop has a memory reference. What’s more, you might have extra memory references as the stack spills over into main memory. —> optimization:by keeping the top N elements in registers, and memory references are made only when register stack overflows or underflows.
Stack size can influence the efficiency.

Classes of Instructions

  • Data Transfer
    • LD, ST, MFC1, MTC1, MFC0, MTC0
  • ALU
    • ADD, SUB, AND, OR, XOR, MUL, DIV, SLT, LUI
  • Control Flow
    • BEQZ, JR, JAL, TRAP, ERET
  • Floating Point
    • ADD.D, SUB.S, MUL.D, C.LT.D, CVT.S.W
  • Multimedia (SIMD)
    • ADD.PS, SUB.PS, MUL.PS, C.LT.PS
  • String
    • REP MOVSB (x86)(copy one string into another string)

Addressing Model

ISA Encoding

variable length, fixed length, VLIW (Very Long Instruction Word)

Microcoded Microarchitecture